This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention that are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
As most people are aware, satellite television systems have become much more widespread over the past few years. In fact, since the introduction of digital satellite television in 1994, more than twelve million American homes have become satellite TV subscribers. Most of these subscribers live in single-family homes where satellite dishes are relatively easy to install and connect. For example, the satellite dish may be installed on the roof of the house. In order to continue this growth, the customer often expects more every year from the service. The service providers thus are constantly considering new features and upgrades such as recording, multi-room operation, and larger and better content. Recently, more attention has become focused on high definition video and audio signals.
High definition signals require more capacity or bandwidth than the services currently provided on the satellite system. Also, many high definition services are provided in addition to, rather than as a replacement to, the current service. In order to provide these new services, some service providers are increasing the total capacity of their systems. Capacity can be increased in a number of ways including increasing the number of transponders or satellite channels available or increasing the number of satellites used. The largest change to the satellite system involves changing the actual communications system specifications.
Recent advances in technology have allowed satellite service providers to consider increasing capacity by changing the system specifications in a number of ways including using a new decoding algorithm such as one created by the Motion Picture Entertainment Group (MPEG) commonly known as MPEG-4. Additionally, it is possible to utilize a more advanced modulation format such as eight level phase shift keying (8PSK) found in the standard created for digital video broadcast (DVB), known as DVB-S2. The DVB-S2 standard also provides for a new error correction system known as low density parity check (LDPC) coding, which allows a further increase in overall system capacity. Although these changes can increase capacity in the communications system, they also change the operating margins for receiving the signal and force changes in the receiver design.
Almost all communications systems, and particularly digital systems such as the satellite system described, employ some form of error correction method to improve receiver performance. These schemes can involve very complex functions that must be carried out at either the transmitter or receiver or both. As mentioned, one such scheme becoming prevalent is LDPC coding.
LDPC coding is a method of error correction that creates parity bits for small sections of a larger segment of a data stream, and appends these to the data stream. The data stream segment operated on may be quite large, for instance 64,800 bits, and parity bits may be created for much smaller sections, such as 3 bits in a group.
Although the processing is performed on segments of the data stream, the incoming data stream remains continuous. The incoming data stream is typically a video or audio signal in a digital form, so the processing must be completed in a finite amount of time. The time allotted for processing the data stream segment is typically referred to as the LDPC frame time. In addition, the parity groups may overlap, where a single bit may be a member of more than one parity group and therefore may have more than one parity bit responsible for the data bit's parity. The method of assigning these groups and parity bits is typically known and predetermined in order for the decoder, and in particular the controller for the decoder, to properly manage the parity checking process.
LDPC decoding may have several layers of processing complexity. A first and very simple parity operation can be performed on the data stream now containing the appended parity bits. The simple parity operation involves simply performing a conventional parity check based on the parity of the parity group and its associated parity bit. If an error is found, then it may be corrected based on the results of the parity group checking. However, it is possible that some errors remain uncorrectable because the exact bit that is in error may still be indeterminable. In order to further address performance of error correction, the same data bit is often used in more than one parity grouping.
Even with both simple parity and multiple group parity, all errors may still not be explicitly corrected. Additionally, due to the nature of the parity groupings, each bit contains not only information about its value intrinsically, but also extrinsically. The intrinsic information about the data bit may be characterized in terms of the actual value of the bit, including knowledge gained by performing parity check operations using the parity information. Extrinsic information involves information that can be determined about the value of the bit, based on values of other data bits in the data stream (e.g., data bits adjacent to the current data bit under process or other bits in the parity groupings.) Using both intrinsic and extrinsic information requires a more complex correction algorithm that involves using both elements of information in an iterative process in order to ascertain the final correct bit value.
The decoder for LDPC coding performs a series of iterations on the received data in order to remove errors from the received data. These iterations consist of two primary steps. The first is called the check node calculation, where data is read from a memory and some arithmetic operations are performed. The results are then written back into the memory. The circuit that performs this first operation is the check node processing unit (CPU). The second step is called the bit node calculation where other data is read from memory and additional arithmetic operations are performed. The results are again written back into memory. The circuit that performs this operation is called the bit node processing unit (BPU). Each of these processing units performs complex calculations that require both processing power and a large local register memory storage for intermediate results. Also, the result of one CPU operation is used in the next BPU operation and vice versa, so each processor is acting on the same data stream segment and only one processing block can operate at a time.
The LDPC codes are constructed so that many of these calculations can be done in parallel on a long segment of the incoming data stream. One current implementation consists of 360 parallel calculation block units processing a bit stream segment that is 64,800 bits long. As mentioned, an LDPC decoder utilizing this type of algorithm must be required to iterate through its process a number of times. Typically a decoder iterates between them as many as 50 or more times in order to determine the final error corrected values for incoming data. And as mentioned, a CPU operation and a BPU operation can never be done at the same time because the BPU operation may depend on changes made during the previous CPU operation and vice versa.
Each of the 360 blocks has the same or similar bit connections relative to each other. This similarity allows for a decoder architecture that permits 360 parallel calculation units. In order to decode the data, there is a circuit block that is responsible for getting 360 pieces of data for the calculation units. For each step, this data comes from a different set of locations in memory.
Although the performance of LDPC codes may exceed preceding error correction methods, the decoder required for an LDPC code is much larger than older systems and further requires multiple iterations through its processing path. The error correction performance is determined, and limited, by the number of iterations that can be made through the processing path in a given timeframe, the LDPC frame time. Structural limitations, including memory allocation, and memory access processing may place an overall restriction on performance of the decoder.
Increasing the number of iterations that can be performed in an LDPC frame time may directly result in improved decoder performance. A circuit architecture and method that increases the number of iterations that can be performed during an LDPC frame time are therefore desirable. Similarly it is desirable to provide an efficient use of resources, such as memory, when constructing the decoder in order to save both size and power, and also increase decoder performance.